Intel QuickPath Interconnect

Intel QuickPath Interconnect (QPI), a Point-to-Point high-speed line-up launched in November 2008, is Intel's equivalent and response to HyperTransport used on AMD processors since 2003; The successor to FSB for Core i3, Core i5, Core i7, Itanium and Xeon. The "QuickPath" bus features an integrated memory controller and improved communication links between system components, which greatly enhances overall system performance. All signal lines previously used on the FSB have been removed and replaced with internally transmitted messages, simplifying the QPI architecture. For the first time, this link was introduced in Intel Core i7-9xx microprocessors and X58 chipsets in November 2008, four months later in Xeon microarchitecture Nehalem, and another 11 months in Itanium processors codenamed Tukwila.

QuickPath is a Point-to-Point connection consisting of one clock line and 20 data lines for each transmission direction, giving a total of 42 signal lines, and since each line is a pair of wires, QPI forms an 82- pin. Each of the 20-line rails is divided into 4 groups (called quadrants) of 5 lines, followed by transfers in 80-bit units called flow control units, consisting of 8 error detection bits, 8 header bits and 64 bits of data transferred in 4 transfers, 2 for each of 2 clock cycles (8 + 8 + 64 → 20 × 2 × 2).

The initial QPI implementations included only one 4-quadrant connection, but the specification also allowed for other configurations. Each quadrant can be used independently, and in high availability servers, QPI can work even in safe mode. If one or more of the 20 + 1 link lines are damaged, the interface may start to operate in 10 + 1 or 5 + 1 mode using the remaining lines operating correctly, and may even transfer the damaged clock line to one of the data lines.

For clock speeds, 2.4 GHz, 2.93 GHz, 3.2 GHz, 4.0 GHz or 4.8 GHz are used. Bandwidth is determined by having only 64 bits of data for each of the 80-bit units, and since they are transmitted in 2 clock cycles, 32 bits are sent in each of them. Based on this information, you can specify that a typical 3.2 GHz QPI link transmitting 32 bits per cycle and transmitting in both directions simultaneously achieves a bandwidth of 25.6 GB / s (3.2 × 32 × 2 = 204, 8 Gb / s = 25.6 GB / s). This value is twice the bandwidth of the 1.6 GHz FSB bus used in the X48 chipset.

The QPI link will be replaced by Intel UltraPath Interconnect (UPI) on Xeon microarchitecture Skylake EX / EP based on the LGA 3647 socket.

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